映像信号処理回路

Image signal processing circuit

Abstract

PROBLEM TO BE SOLVED: To prevent degradation in image quality after an A/D conversion. SOLUTION: Delay circuits are connected in a multistage to delay input synchronous signals by a predetermined delay time (2 to 3 ns). The delayed synchronous signals are inputted to a multistage synchronous signal delay circuit 1 which outputs the delayed synchronous signals for every delay circuit. Then, one delayed synchronous signal is successively selected by a CPU 6 and a selecting circuit 2 and the selected signal is supplied to a PLL circuit 3. The circuit 3 generates a sampling clock having N times frequency (where N is an integer) of the frequency of the delayed synchronous signal that is the reference of the image signal processing based on the delayed synchronous signal. Then, the clock is used to covert the image signals to digital video signals by an A/D converting circuit 4 and the signals are stored in a storage circuit 5. Every time when the delayed synchronous signal is selected, the CPU 6 reads the digital video signal at the time of the previous delayed synchronous signal from the storage circuit 5, computes the difference between the digital video signal at the current delayed synchronous signal and the digital video signal at the previous delayed synchronous signal. When the difference becomes a minimum, the selected signal at that time is held as the optimum delayed synchronous signal and the reference sampling clock for the video signal processing is determined by the above-mentioned synchronous signal. COPYRIGHT: (C)1998,JPO
(57)【要約】 【課題】 A/D変換後の映像品質の劣化を防止する。 【解決手段】 入力同期信号を予め決められた遅延時間 (2〜3ns)だけ遅延させる遅延回路を多段接続し、 その遅延回路毎に遅延同期信号を出力する多段同期信号 遅延回路1に入力し、CPU6と選択回路2により順次 1つの遅延同期信号を選択してPLL回路3に供給し、 ここで遅延同期信号を基に映像信号処理の基準となる遅 延同期信号の周波数のN倍(Nは整数)の周波数のサン プリングクロックを生成し、このサンプリングクロック で映像信号をA/D変換回路4でデジタル映像信号に変 換し、記憶回路5に記憶する。CPU6はそれぞれの遅 延同期信号を選択する度に前回の遅延同期信号のときの デジタル映像信号を前記記憶回路から読み出し、今回の 遅延同期信号におけるデジタル映像信号との差を算出 し、この差が最小になったときの遅延同期信号を最適な 遅延同期信号として、そのときの選択信号を保持するこ とにより前記同期信号により映像信号処理の基準サンプ リングクロックを決定する。

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    Publication numberPublication dateAssigneeTitle
    JP-2001249637-ASeptember 14, 2001Nec Mitsubishi Denki Visual Systems Kk, エヌイーシー三菱電機ビジュアルシステムズ株式会社表示装置
    US-8149331-B2April 03, 2012Gvbb Holdings S.A.R.LDelay stabilization method and apparatus for video format conversion