Simulated response signal outputting circuit

模擬応答信号出力回路

Abstract

PROBLEM TO BE SOLVED: To attain address setting despite of the address of an input and output circuit to be simulated by outputting a simulated response signal when a prescribed time elapses while a response signal is not outputted from an original inputting and outputting function circuit. SOLUTION: An address which is the same as the upper and lower limit addresses of the whole address space of a system is set in an address setting circuit 10. When an input and output to which an address corresponding to an address signal ADD outputted from a CPU is allocated is present, an acknowledge signal ACK is outputted by itself for a response. On the other hand, when any input and output to which the address corresponding to the address signal ADD is allocated is not present, a simulated response signal is outputted, and the acknowledge signal ACK is outputted from an acknowledge signal monitoring circuit 15 at the time-up point of a time count circuit 16. Thus, it is possible to facilitate a counter measure to the entire address space of this system by preparing the simulated response signal output being a simulated response signal outputting circuit having only one address setting circuit.
(57)【要約】 【課題】 模擬対象の入出力回路のアドレスには拘らず にアドレス設定が可能な模擬応答信号出力回路が求めら れている。 【解決手段】 アドレス信号によりアクセスされて応答 信号を出力する一つまたは複数の入出力機能回路が割り 付けられたアドレス空間内の全アドレスが設定されてお り、アドレス信号の値がアドレス空間の範囲内である場 合にアドレス判別信号11を出力するアドレス設定回路10 と、アドレス判別信号11の出力により計時を開始し、ア ドレス信号に対応していずれかの入出力機能回路からの アクノリッジ信号ACK の出力により計時を終了するタイ ムカウント回路16と、アドレス信号に対していずれの入 出力機能回路からもアクノリッジ信号ACK が出力されな い内にタイムカウント回路16が所定時間の計時を完了し た場合に、模擬的なアクノリッジ信号ACK を出力するア クノリッジ信号生成回路13とを備える。

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