エピタキシャル半導体ウエハの特性測定方法

Measurement of characteristics of epitaxial semiconductor wafer

Abstract

(57)【要約】 【課題】本発明の課題は半導体基板ウエハへのエピタキ シャル膜成長の際における製品ウエハの抵抗値管理およ び製品歩留まりを向上させるべく高精度の直接抵抗測定 を実現できるエピタキシャル半導体ウエハの特性測定方 法を提供することである。 【解決手段】上記課題を解決するために、この発明にか かる特性測定方法は、通常使用されるエピタキシャル成 長層が基板と同じ導電型であり、それらの間に異なる導 電型の層を介在させることによって測定電流のリークを 阻止できる点に着目したものであって、半導体基板上に エピタキシャル層を形成し、前記半導体基板と前記エピ タキシャル層との間に前記エピタキシャル層と異なる導 電型の埋込拡散層を形成し、前記埋込拡散層の上方で、 かつ前記エピタキシャル層に通電して前記エピタキシャ ル層の抵抗測定を行うことを特徴とする。
PROBLEM TO BE SOLVED: To make it possible to take directly a high-accuracy measurement of a resistance to a substrate wafer by current conduction in an epitaxial layer, by a method wherein a buried diffused layer of a conductivity type different from that of the epitaxial layer is made to interpose between the semiconductor substrate and the epitaxial layer to prevent a measurement current from leaking to the side of the substrate. SOLUTION: A buried layer 3 consisting of a P-type diffused layer is formed between a substrate wafer 1 and an N-type epitaxial layer 2. The probes 5 to 8 of a four-probe method measuring device 4 with four proves 5 to 8 arranged at equal intervals on a straight line are applied to the surface of the layer 2 over the layer 3 to measure the resistance of the wafer 1. That is, a constant current is made to flow through the probes 5 and 8, a voltage between the probes 6 and 7 is measured and the specific resistance of the layer 2 is found by an arithmetic expression from the measured value of the voltage. Accordingly, as a measurement current is prevented from flowing out to the side of the wafer 1 by the layer 3 and is made to flow through the surface layer of the layer 2, the specific resistance of the layer 2 itself can be measured with high accuracy.

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