Scrmos à haute tension dans des technologies de processus bicmos

High voltage scrmos in bicmos process technologies

Abstract

An integrated circuit includes an SCRMOS transistor formed with a reduced surface field (RESURF) region (1024) around a drain region (1010) and an SCR terminal (1012). The RESURF region is the same conductivity type and more heaviliy doped than a drift region (1014).
Selon l'invention, un circuit intégré comprend un transistor SCRMOS formé avec une zone de champ à surface réduite (RESURF) (1024) autour d'une zone de drain (1010) et une borne SCR (1012). La zone RESURF est du même type de conductivité et plus lourdement dopée qu'une zone de dérive (1014).

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Patent Citations (4)

    Publication numberPublication dateAssigneeTitle
    US-2002135016-A1September 26, 2002Koninklijke Philips Electronics N.V.Field effect transistor structure and method of manufacture
    US-2003027396-A1February 06, 2003Semiconductor Components Industries, Llc.Method for manufacturing a high voltage MOSFET semiconductor device with enhanced charge controllability
    US-2007126057-A1June 07, 2007Jing-Meng Liu, Hung-Der SuLateral DMOS device insensitive to oxide corner loss
    US-2009166721-A1July 02, 2009Marie Denison, Pinghai HaoQuasi-vertical gated npn-pnp esd protection device

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    JP-2014525147-ASeptember 25, 2014无錫華潤上華半導体有限公司Csmc Technologies Fab1 Co., Ltd静電気放電保護構造及びその製造方法